View LT19431_4866700.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lt1943 1 1943fa features applicatio s u descriptio u typical applicatio u 4 integrated switches: 2.4a buck, 2.6a boost, 0.35a boost, 0.35a inverter (guaranteed minimum current limit) fixed frequency, low noise outputs soft-start for all outputs externally programmable v on delay integrated schottky diode for v on output pgood pin for av dd output disconnect 4.5v to 22v input voltage range panelprotect tm circuitry disables v on upon fault available in thermally enhanced 28-lead tssop high current quad output regulator for tft lcd panels , ltc and lt are registered trademarks of linear technology corporation. quad output tft-lcd power supply the lt ? 1943 quad output adjustable switching regulator provides power for large tft lcd panels. the device, housed in a low profile 28 pin thermally enhanced tssop package, can generate a 3.3v or 5v logic supply along with the triple output supply required for the tft lcd panel. operating from an input range of 4.5v to 22v, a step-down regulator provides a low voltage output v logic with up to 2a current. a high-power step-up converter, a lower- power step-up converter and an inverting converter pro- vide the three independent output voltages av dd , v on and v off required by the lcd panel. a high-side pnp provides delayed turn-on of the v on signal and can handle up to 30ma. protection circuitry ensures that v on is disabled if any of the four outputs are more than 10% below the programmed voltage. all switchers are synchronized to an internal 1.2mhz clock, allowing the use of low profile inductors and ce- ramic capacitors throughout. a current mode architecture provides excellent transient response. for best flexibility, all outputs are adjustable. soft-start is included in all four channels. a pgood pin can drive an optional pmos pass device to provide output disconnect for the av dd output. v c2 v c3 sw4 nfb4 fb4 bias boost sw1 fb1 v c1 sw2 fb2 run-ss ss-234 c t pgood v on e3 fb3 gnd sgnd lt1943 v in sw3 6.8k 18k 27k 2.2nf 2.2nf 680pf 100pf 100pf 100pf 16.2k 10.0k 10.0k 44.2k 274k 10.0k 10pf 10.0k 4.7 h 0.22 f v logic 3.3v 2a 10 f 0.47 f 1 f v off C5.5v 50ma 10 h 33 h 10 h 10 h 88.7k 10 f 2.2 f 0.47 f 13k 2.2nf 100pf av dd 12.2v 500ma pgood v on 35v 30ma 1943 ta01 2.2 f v in, 8v to 20v 22 f 0.015 f 0.015 f 0.047 f v c4 av dd 10v/div run-ss 2v/div v logic 5v/div i in(avg) 1a/div v off 10v/div v e3 20v/div v on 50v/div 5ms/div startup waveforms panelprotect is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. large tft-lcd desktop monitors flat panel televisions
lt1943 2 1943fa parameter conditions min typ max units minimum input voltage 4.5 v maximum input voltage 22 v quiescent current not switching 10 14 ma run-ss = ss-234 = 0v 35 45 a run-ss, ss-234 pin current run-ss, ss-234 = 0.4v 1.7 a run-ss, ss-234 threshold 0.8 v bias pin voltage to begin ss-234 charge 2.4 2.8 3.15 v bias pin current bias = 3.1v, all switches off 10.5 15 ma fb threshold offset to begin c t charge (note 3) 90 125 160 mv c t pin current source all fb pins = 1.5v 16 20 25 a c t threshold to power v on all fb pins = 1.5v 1.0 1.1 1.2 v v on switch drop v on current = 30ma 180 240 mv maximum v on current v e3 = 30v 30 60 ma pgood threshold offset 90 125 160 mv pgood sink current 200 a pgood pin leakage v pgood = 36v 1 a master oscillator frequency 1.1 1.2 1.35 mhz 1.0 1.46 mhz foldback switching frequency all fb pins = 0v 250 khz frequency shift threshold on fb ? 200khz 0.5 v v in voltage .............................................................. 25v boost voltage ........................................................ 36v boost voltage above sw1 ..................................... 25v bias pin voltage ..................................................... 18v sw2, sw4 pin voltages .......................................... 40v sw3 voltage ............................................................ 40v fb1, fb2, fb3, fb4 voltages ...................................... 4v nfb4 voltage ................................................ +6v, C0.6v vc1, vc2, vc3, vc4 pin voltages .............................. 6v run-ss, ss-234 pin voltages ................................... 6v pgood pin voltage ................................................. 36v e3 pin voltage ......................................................... 38v v on voltage ............................................................. 38v c t pin voltage ........................................................... 6v junction temperature ........................................... 125 c operating temperature range (note 2) ...C40 c to 85 c storage temperature range ..................C65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 125 c, ja = 25 c/w, jc = 7.5 c/w lt1943efe absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 12v, run-ss, ss-234 = 2.5v unless otherwise noted. consult ltc marketing for parts specified with wider operating temperature ranges. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd vc1 vc2 fb1 fb2 fb3 nfb4 fb4 vc3 vc4 sgnd boost sw1 sw1 sw2 sw2 v on c t e3 pgood bias sw3 gnd sw4 run-ss ss-234 v in v in fe package 28-lead plastic tssop exposed pad (pin 29) is ground (must be soldered to pcb) 29 fe part marking 1943e
lt1943 3 1943fa electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 12v, run-ss, ss-234 = 2.5v unless otherwise noted. parameter conditions min typ max units switch 1 (2.4a buck) fb1 voltage 1.23 1.25 1.27 v 1.22 1.27 v fb1 voltage line regulation 4.5v < v in < 22v 0.01 0.03 %/v fb1 pin bias current (note 4) 100 600 na error amplifier 1 voltage gain 200 v/v error amplifier 1 transconductance ? i = 5 a 450 mhos switch 1 current limit duty cycle = 35% (note 6) 2.4 3.2 4.3 a switch 1 v cesat i sw = 2a 310 470 mv switch 1 leakage current fb1 = 1.5v 0.1 10 a minimum boost voltage above sw1 pin i sw = 1.5a (note 7) 1.8 2.5 v boost pin current i sw = 1.5a 30 50 ma maximum duty cycle (sw1) 82 92 % switch 2 (2.6a boost) fb2 voltage 1.23 1.25 1.27 v 1.22 1.27 v fb2 voltage line regulation 4.5v < v in < 22v 0.01 0.03 %/v fb2 pin bias current (note 4) 220 1000 na error amplifier 2 voltage gain 200 v/v error amplifier 2 transconductance ? i = 5 a 450 mhos switch 2 current limit 2.6 3.8 4.9 a switch 2 v cesat i sw2 = 2a 360 540 mv switch 2 leakage current fb2 = 1.5v 0.1 1 a bias pin current i sw2 = 2a 45 ma maximum duty cycle (sw2) 85 92 % switch 3 (350ma boost) fb3 voltage 1.23 1.25 1.27 v 1.22 1.27 v fb3 voltage line regulation 4.5v < v in < 22v 0.01 0.03 %/v fb3 pin bias current (note 4) 100 600 na error amplifier 3 voltage gain 200 v/v error amplifier 3 transconductance ? i = 5 a 450 mhos switch 3 current limit 0.35 0.5 0.7 a switch 3 v cesat i sw3 = 0.2a 180 280 mv switch 3 leakage current fb3 = 1.5v 0.1 1 a bias pin current i sw3 = 0.2a 14 ma maximum duty cycle (sw3) 84 88 % 83 % schottky diode drop i = 170ma 700 mv
lt1943 4 1943fa the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. run-ss, ss-234 = 2.5v unless otherwise noted. electrical characteristics parameter conditions min typ max units switch 4 (350ma inverter) fb4 voltage 1.23 1.25 1.27 v 1.22 1.27 v fb4 voltage line regulation 4.5v < v in < 22v 0.01 0.03 %/v fb4 pin bias current (note 4) 100 600 na nfb4 voltage (v fb4 -v nfb4 ) 1.215 1.245 1.275 v 1.205 1.275 v nfb4 voltage line regulation 4.5v < v in < 22v 0.01 0.03 %/v nfb4 pin bias current (note 5) 100 600 na error amplifier 4 voltage gain 200 v/v error amplifier 4 transconductance ? i = 5 a 450 mhos switch 4 current limit 0.35 0.5 0.7 a switch 4 v cesat i sw4 = 0.3a 260 390 mv switch 4 leakage current fb4 = 1.5v 0.1 1 a bias pin current due to sw4 i sw4 = 0.3a 15 ma maximum duty cycle (sw4) 84 88 % 83 % typical perfor a ce characteristics uw duty cycle (%) 0 sw1 current (a) 5 4 3 2 1 0 20 40 60 80 1943 g02 100 temperature ( c) C50 sw1 current (a) 4.5 4.0 3.5 3.0 2.5 0 50 75 1943 g03 C25 25 100 125 input voltage (v) 0 v logic maximum output current (a) 2.0 2.2 2.4 20 1943 g01 1.8 1.6 1.2 5 10 15 1.4 2.8 2.6 l1 = 4.7 h l1 = 3.3 h typical minimum t a = 25 c t a = 25 c maximum output current for v logic = 3.3v sw1 current limit vs duty cycle sw1 current limit note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the lt1943e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization, and correlation with statistical process controls. note 3: the c t pin is held low until fb1, fb2, fb3 and fb4 all ramp above the fb threshold offset. note 4: current flows into fb1, fb2, fb3 and fb4 pins. note 5: current flows out of nfb4 pin. note 6: current limit is guaranteed by design and/or correlation to static test. slope compensation reduces current limit at high duty cycle. note 7: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch.
lt1943 5 1943fa typical perfor a ce characteristics uw sw3 current (a) 0 sw3 voltage drop (mv) 0.4 1943 g11 0.1 0.2 0.3 0 0.4 0.1 0.2 0.3 500 400 300 200 100 0 500 400 300 200 100 0 sw4 current (a) sw4 voltage drop (mv) 1943 g12 sw2 current (a) 0 sw2 voltage drop (mv) 600 500 400 300 200 100 0 0.5 1.0 1.5 2.0 1943 g10 2.5 3.0 sw1 current (a) 0 sw1 voltage drop (mv) 600 500 400 300 200 100 0 0.5 1.0 1.5 2.0 1943 g09 2.5 3.0 temperature ( c) C50 sw3 current (a) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.8 0.7 0.6 0.5 0.4 0.3 0.2 25 75 1943 g07 C25 0 50 100 125 temperature ( c) C50 sw4 current (a) 25 75 1943 g08 C25 0 50 100 125 temperature ( c) C50 sw2 current (a) 5.0 4.5 4.0 3.5 3.0 2.5 0 50 75 1943 g06 C25 25 100 125 sw1 current (a) 0 boost pin current (ma) 100 80 60 40 20 0 0.5 1.0 1.5 2.0 1943 g05 2.5 3.0 load current (ma) 0 input voltage (v) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 20 40 60 80 1943 g04 100 t a = 25 c t a = 25 c t a = 25 c t a = 25 c t a = 25 c t a = 25 c minimum input voltage to start, v logic = 3.3v sw4 v cesat sw3 v cesat sw2 v cesat sw1 v cesat sw4 current limit sw3 current limit boost pin current sw2 current limit
lt1943 6 1943fa v on (v) 5 100 90 80 70 60 50 40 30 20 30 1943 g13 1943 g14 10 15 25 35 40 v on current (ma) 1.4 1.3 1.2 1.1 1.0 frequency (mhz) feedback voltage (v) switching frequency (mhz) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1943 g15 0 0.2 0.4 0.6 0.8 1.0 1.2 temperature ( c) C50 C25 0 25 50 75 125 100 temperature ( c) C50 reference voltage (v) 1.27 1.26 1.25 1.24 1.23 1.22 25 75 1943 g16 C25 0 50 100 125 temperature ( c) C50 bias pin current (ma) 100 80 60 40 20 0 25 75 1943 g17 C25 0 50 100 125 i sw2 = 1.5a i sw3 = 0.2a i sw4 = 0.3a i sw2 = i sw3 = i sw4 = 0a t a = 25 c t a = 25 c load current (a) 0 efficiency (%) 100 90 80 70 60 50 0.4 1943 g18 0.1 0.2 0.3 0.5 load current (a) 0 efficiency (%) 100 90 80 70 60 50 0.25 0.50 0.75 1.00 1943 g19 1.25 1.50 v in = 5v t a = 25 c v in = 5v t a = 25 c typical perfor a ce characteristics uw v on current limit bias pin current reference voltage frequency foldback oscillator frequency efficiency, av dd = 13v efficiency, v logic = 3.3v
lt1943 7 1943fa gnd (pins 1, 20, exposed pad pin 29): ground. tie both gnd pins and the exposed pad directly to a local ground plane. the ground metal to the exposed pad should be as wide as possible for better heat dissipation. multiple vias (to ground plane under the ground backplane) placed close to the exposed pad can further aid in reducing thermal resistance. vc1 (pin 2): switching regulator 1 error amplifier com- pensation. connect a resistor/capacitor network in series with this pin. vc2 (pin 3): error amplifier compensation for switcher 2. connect a resistor/capacitor network in series with this pin. fb1 (pin 4): switching regulator 1 feedback. tie the resistor divider tap to this pin and set v logic according to v logic = 1.25 ? (1 + r2/r1). reference designators refer to figure 1. fb2 (pin 5): feedback for switch 2. tie the resistor divider tap to this pin and set av dd according to av dd = 1.25 ? (1 + r6/r5). fb3 (pin 6): switching regulator 3 feedback. tie the resistor divider tap to this pin and set v on according to v on = 1.25 ? (1 + r9/r8) C 150mv. nfb4 (pin 7): switching regulator 4 negative feedback. switcher 4 can be used to generate a positive or negative output. when regulating a negative output, tie the resistor divider tap to this pin. negative output voltage can be set by the equation v off = C1.245 ? (r3/r4) with r4 set to 10k. tie the nfb4 pin to fb4 for positive output voltages. fb4 (pin 8): feedback for switch 4. when generating a positive voltage from switch 4, tie the resistor divider tap to this pin. when generating a negative voltage, tie a 10k resistor between fb4 and nfb4 (r4). vc3 (pin 9): switching regulator 3 error amplifier com- pensation. connect a resistor/capacitor network in series with this pin. vc4 (pin 10): switching regulator 4 error amplifier compensation. connect a resistor/capacitor network in series with this pin. sgnd (pin 11): signal ground. return ground trace from the fb resistor networks and v c pin compensation compo- nents directly to this pin and then tie to ground. boost (pin 12): the boost pin is used to provide a drive voltage, higher than v in , to the switch 1 drive circuit. sw1 (pins 13, 14): the sw1 pins are the emitter of the internal npn bipolar power transistor for switching regu- lator 1. these pins must be tied together for proper operation. connect these pins to the inductor, catch diode and boost capacitor. v in (pins 15, 16): the v in pins supply current to the lt1943s internal regulator and to the internal power transistor for switch 1. these pins must be tied together and locally bypassed. ss-234 (pin 17): this is the soft-start pin for switching regulators 2, 3 and 4. place a soft-start capacitor here to limit start-up inrush current and output voltage ramp rate. when the bias pin reaches 2.8v, a 1.7 a current source begins charging the capacitor. when the capacitor voltage reaches 0.8v, switches 2, 3 and 4 turn on and begin switching. for slower start-up, use a larger capacitor. when this pin is pulled to ground, switches 2, 3 and 4 are disabled. for complete shutdown, tie run-ss to ground. run-ss (pin 18): this is the soft-start pin for switching regulator 1. place a soft-start capacitor here to limit start- up inrush current and output voltage ramp rate. when power is applied to the v in pin, a 1.7 a current source charges the capacitor. when the voltage at this pin reaches 0.8v, switch 1 turns on and begins switching. for slower start-up, use a larger capacitor. for complete shutdown, tie run-ss to ground. sw4 (pin 19): this is the collector of the internal npn bipolar power transistor for switching regulator 4. mini- mize metal trace area at this pin to keep emi down. uu u pi fu ctio s
lt1943 8 1943fa sw3 (pin 21): this is the collector of the internal npn bipolar power transistor for switching regulator 3. mini- mize metal trace area at this pin to keep emi down. bias (pin 22): the bias pin is used to improve efficiency when operating at higher input voltages. connecting this pin to the output of switching regulator 1 forces most of the internal circuitry to draw its operating current from v logic rather than v in . the drivers of switches 2, 3 and 4 are supplied by bias. switches 2, 3 and 4 will not switch until the bias pin reaches approximately 2.8v. bias must be tied to v logic . pgood (pin 23): power good comparator output. this is the open collector output of the power good comparator and can be used in conjunction with an external p-channel mosfet to provide output disconnect for av dd as shown in the 5v input, quad output tft-lcd power supply on the last page of the data sheet. when switcher 2s output reaches approximately 90% of its programmed voltage, pgood will be pulled to ground. this will pull down on the gate of the mosfet, connecting av dd . a 100k pull-up resistor between the source and gate of the p-channel mosfet keeps it off when switcher 2s output is low. e3 (pin 24): this is switching regulator 3s output and the emitter of the output disconnect pnp. tie the output capacitor and resistor divider here. c t (pin 25): timing capacitor pin. this is the input to the v on timer and programs the time delay from all four feedback pins reaching 1.125v to v on turning on. the c t capacitor value can be set using the equation c = (20 a ? t delay )/1.1v. v on (pin 26): this is the delayed output for switching regulator 3. v on reaches its programmed voltage after the internal c t timer times out. protection circuitry ensures v on is disabled if any of the four outputs are more than 10% below normal voltage. sw2 (pins 27, 28): the sw2 pins are the collector of the internal npn bipolar power transistor for switching regu- lator 2. these pins must be tied together. minimize trace area at these pins to keep emi down. uu u pi fu ctio s
lt1943 9 1943fa block diagra w figure 1. block diagram C + C + sq r driver 400ma switch slope compensation foldback oscillator 21 6 1 9 C + C + C + sq r driver 400ma switch slope compensation foldback oscillator 19 17 10 C + C + C C C C + sq r driver 2.6a switch slope compensation foldback oscillator 27 28 22 25 5 23 15 26 3 C + C + sq r driver 2.4a switch slope compensation foldback oscillator 2 12 4 gm gm gm gm 1.25v 1.25v fb3 gnd 11 sgnd 20 gnd 29 gnd ss-234 run-ss r8 r9 master oscillator 1.2mhz C + v c4 v c3 sw3 e3 v e3 v c2 v c1 bias sw2 8 fb4 7 nfb4 sw4 v on v on v e3 1.1v 1.125v C + 1.12v 1.25v 1.25v c t fb2 fb1 v logic pgood 20 a 16 v in v in boost internal regulator and reference sw2 sw3 sw4 lockout 1.7 a 1.7 a bias 2.8v v in 18 c4 c15 c10 c22 c7 c6 c13 c5 24 r3 r4 r12 c23 c14 c24 r13 c21 c12 r11 c20 c11 r10 l5 v in v logic v logic v off c16 c8 c1 c9 v in av dd c2 l1 c3 d2 d1 l2 14 13 sw1 d3 d6 d5 l4 l3 r5 r6 r14 r1 r2 av dd C +
lt1943 10 1943fa operatio u figure 2. lt1943 power-up sequence. (traces from both photos are synchronized to the same trigger) run-ss 2v/div v logic 5v/div i l1 1a/div i l2+l3 1a/div ss-234 2v/div av dd 20v/div pgood 20v/div 5ms/div 1943 f03a v off 10v/div v ct 2v/div i l4 500ma/div i l5 500ma/div v e3 20v/div v on 50v/div 5ms/div 1943 f03b (2a) (2b) the lt1943 is a highly integrated power supply ic con- taining four separate switching regulators. all four switch- ing regulators have their own oscillator with frequency foldback and use current mode control. switching regula- tor 1 consists of a step-down regulator with a switch current limit of 2.4a. switching regulator 2 can be config- ured as a step-up or sepic converter and has a 2.6a switch. switching regulator 3 consists of a step-up regu- lator with a 0.35a switch as well as an integrated schottky diode. switching regulator 4 has two feedback pins (fb4 and nfb4) and can directly regulate positive or negative output voltages. the four regulators share common cir- cuitry including input source, voltage reference, and mas- ter oscillator. operation can be best understood by refer- ring to the block diagram as shown in figure 1. if the run/ss pin is pulled to ground, the lt1943 is shut down and draws 35 a from the input source tied to v in . an internal 1.7 a current source charges the external soft- start capacitor, generating a voltage ramp at this pin. if the run/ss pin exceeds 0.6v, the internal bias circuits turn on, including the internal regulator, reference, and 1.1mhz master oscillator. the master oscillator generates four clock signals, one for each of the switching regulators. switching regulator 1 will only begin to operate when the run/ss pin reaches 0.8v. switcher 1 generates v logic , which must be tied to the bias pin. when bias reaches 2.8v, the npn pulling down on the ss-234 pin turns off, allowing an internal 1.7 a current source to charge the external capacitor tied to the ss-234 pin. when the voltage on the ss-234 pin reaches 0.8v, switchers 2, 3 and 4 are enabled. av dd and v off will then begin rising at a ramp rate determined by the capacitor tied to the ss-234 pin. when all the outputs reach 90% of their programmed voltages, the npn pulling down on the c t pin will turn off, and an internal 20 a current source will charge the exter- nal capacitor tied to the c t pin. when the c t pin reaches 1.1v, the output disconnect pnp turns on, connecting v on . in the event of any of the four outputs dropping below 10% of their programmed voltage, panelprotect circuitry pulls the c t pin to gnd, disabling v on . a power good comparator monitors av dd and turns on when the fb2 pin is at or above 90% of its regulated value. the output is an open collector transistor that is off when the output is out of regulation, allowing an external resis- tor to pull the pin high. this pin can be used with a p-channel mosfet that functions as an output disconnect for av dd . the four switchers are current mode regulators. instead of directly modulating the duty cycle of the power switch, the feedback loop controls the peak current in the switch during each cycle. compared to voltage mode control, current mode control improves loop dynamics and pro- vides cycle-by-cycle current limit.
lt1943 11 1943fa the control loop for the four switchers is similar. a pulse from the slave oscillator sets the rs latch and turns on the internal npn bipolar power switch. current in the switch and the external inductor begins to increase. when this current exceeds a level determined by the voltage at v c , the current comparator resets the latch, turning off the switch. the current in the inductor flows through the schottky diode and begins to decrease. the cycle begins again at the next pulse from the oscillator. in this way, the voltage on the v c pin controls the current through the inductor to the output. the internal error amplifier regulates the output voltage by continually adjusting the v c pin voltage. the threshold for switching on the v c pin is 0.8v, and an active clamp of 1.8v limits the output current. the run/ss and ss-234 pins also clamp the v c pin voltage. as the internal current source charges the external soft-start capacitor, the current limit increases slowly. each switcher contains an extra, independent oscillator to perform frequency foldback during overload conditions. this slave oscillator is normally synchronized to the mas- ter oscillator. a comparator senses when v fb is less than 0.5v and switches the regulator from the master oscillator to a slower slave oscillator. the v fb pin is less than 0.5v during startup, short-circuit, and overload conditions. frequency foldback helps limit switch current and power dissipation under these conditions. the switch driver for sw1 operates either from v in or from the boost pin. an external capacitor and diode are used to generate a voltage at the boost pin that is higher than the input supply. this allows the driver to saturate the internal bipolar npn power switch for efficient operation. step-down considerations fb resistor network the output voltage for switcher 1 is programmed with a resistor divider (refer to the block diagram) between the output and the fb pin. choose the resistors according to: r2 = r1(v out /1.25v C 1) r1 should be 10k ? or less to avoid bias current errors. input voltage range the minimum operating voltage of switcher 1 is deter- mined either by the lt1943s undervoltage lockout of ~4v, or by its maximum duty cycle. the duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: dc = (v out + v f )/(v in C v sw + v f ) where v f is the forward voltage drop of the catch diode (~0.4v) and v sw is the voltage drop of the internal switch (~0.3v at maximum load). this leads to a minimum input voltage of v in(min) = (v out + v f )/dc max C v f + v sw with dc max = 0.82. inductor selection and maximum output current a good first choice for the inductor value is: l = (v out + v f )/1.2 where v f is the voltage drop of the catch diode (~0.4v) and l is in h. the inductors rms current rating must be greater than the maximum load current and its saturation current should be at least 30% higher. for highest effi- ciency, the series resistance (dcr) should be less than 0.1 ? . table 1 lists several vendors and types that are suitable. the optimum inductor for a given application may differ from the one indicated by this simple design guide. a larger value inductor provides a higher maximum load current, and reduces the output voltage ripple. if your load is lower than the maximum load current, then you can relax the value of the inductor and operate with higher ripple current. this allows you to use a physically smaller inductor, or one with a lower dcr resulting in higher efficiency. be aware that the maximum load current depends on input voltage. a graph in the typical perfor- mance section of this data sheet shows the maximum load current as a function of input voltage and inductor value for v out = 3.3v. in addition, low inductance may result in discontinuous mode operation, which further reduces operatio u
lt1943 12 1943fa maximum load current. for details of maximum output current and discontinuous mode operation, see linear technologys application note an44. finally, for duty cycles greater than 50% (v out /v in > 0.5), a minimum inductance is required to avoid subharmonic oscillations. see an19. the current in the inductor is a triangle wave with an average value equal to the load current. the peak switch current is equal to the output current plus half the peak-to- peak inductor ripple current. the lt1943 limits its switch current in order to protect itself and the system from overload faults. therefore, the maximum output current that the lt1943 will deliver depends on the switch current limit, the inductor value, and the input and output voltages. when the switch is off, the potential across the inductor is the output voltage plus the catch diode drop. this gives the peak-to-peak ripple current in the inductor: ? i l = (1 C dc)(v out + v f )/(l ? f), where f is the switching frequency of the lt1943 and l is the value of the inductor. the peak inductor and switch current is i swpk = i lpk = i out + ? i l /2 to maintain output regulation, this peak current must be less than the lt1943s switch current limit of i lim . for sw1, i lim is at least 2.4a at dc = 0.35 and decreases linearly to 1.6a at dc = 0.8, as shown in the typical performance characteristics section. the maximum out- put current is a function of the chosen inductor value: i out(max) = i lim C ? i l /2 = 3a ? (1 C 0.57 ? dc) C ? i l /2 choosing an inductor value so that the ripple current is small will allow a maximum output current near the switch current limit. one approach to choosing the inductor is to start with the simple rule given above, look at the available inductors, and choose one to meet cost or space goals. then use operatio u these equations to check that the lt1943 will be able to deliver the required output current. note again that these equations assume that the inductor current is continuous. discontinuous operation occurs when i out is less than ? i l /2. table 1. inductors. part number value ( h) i rms (a) dcr ( ? ) height (mm) sumida cr43-1r4 1.4 2.52 0.056 3.5 cr43-2r2 2.2 1.75 0.071 3.5 cr43-3r3 3.3 1.44 0.086 3.5 cr43-4r7 4.7 1.15 0.109 3.5 cdrh3d16-1r5 1.5 1.55 0.040 1.8 cdrh3d16-2r2 2.2 1.20 0.050 1.8 cdrh3d16-3r3 3.3 1.10 0.063 1.8 cdrh4d28-3r3 3.3 1.57 0.049 3.0 cdrh4d28-4r7 4.7 1.32 0.072 3.0 cdrh4d18-1r0 1.0 1.70 0.035 2.0 cdc5d23-2r2 2.2 2.50 0.03 2.5 cdrh5d28-2r6 2.6 2.60 0.013 3.0 coilcraft do1606t-152 1.5 2.10 0.060 2.0 do1606t-222 2.2 1.70 0.070 2.0 do1606t-332 3.3 1.30 0.100 2.0 do1606t-472 4.7 1.10 0.120 2.0 do1608c-152 1.5 2.60 0.050 2.9 do1608c-222 2.2 2.30 0.070 2.9 do1608c-332 3.3 2.00 0.080 2.9 do1608c-472 4.7 1.50 0.090 2.9 mos6020-222 2.2 2.15 0.035 2.0 mos6020-332 3.3 1.8 0.046 2.0 mos6020-472 4.7 1.5 0.050 2.0 d03314-222 2.2 1.6 0.200 1.4 1008ps-272 2.7 1.3 0.140 2.7 toko (d62f)847fy-2r4m 2.4 2.5 0.037 2.7 (d73lf)817fy-2r2m 2.2 2.7 0.03 3.0
lt1943 13 1943fa output capacitor selection for 5v and 3.3v outputs, a 10 f 6.3v ceramic capacitor (x5r or x7r) at the output results in very low output voltage ripple and good transient response. other types and values will also work; the following discussion ex- plores tradeoffs in output ripple and transient perfor- mance. the output capacitor filters the inductor current to gener- ate an output with low voltage ripple. it also stores energy in order satisfy transient loads and stabilizes the lt1943s control loop. because the lt1943 operates at a high frequency, minimal output capacitance is necessary. in addition, the control loop operates well with or without the presence of output capacitor series resistance (esr). ceramic capacitors, which achieve very low output ripple and small circuit size, are therefore an option. you can estimate output ripple with the following equations: v ripple = ? i l /(8 ? f ? c out ) for ceramic capacitors, and v ripple = ? i l ? esr for electrolytic capacitors (tantalum and aluminum); where ? i l is the peak-to-peak ripple current in the induc- tor. the rms content of this ripple is very low so the rms current rating of the output capacitor is usually not of concern. it can be estimated with the formula: i c(rms) = ? i l / 12 another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor transfers to the output, the resulting voltage step should be small compared to the regulation voltage. for a 5% overshoot, this requirement indicates: c out > 10 ? l ? (i lim /v out ) 2 the low esr and small size of ceramic capacitors make them the preferred type for lt1943 applications. not all ceramic capacitors are the same, however. many of the higher value capacitors use poor dielectrics with high temperature and voltage coefficients. in particular, y5v and z5u types lose a large fraction of their capacitance with applied voltage and at temperature extremes. because loop stability and transient response depend on the value of c out , this loss may be unacceptable. use x7r and x5r types. electrolytic capacitors are also an option. the esrs of most aluminum electrolytic capacitors are too large to deliver low output ripple. tantalum and newer, lower esr organic electrolytic capacitors intended for power supply use are suitable, and the manufacturers will specify the esr. chose a capacitor with a low enough esr for the required output ripple. because the volume of the capaci- tor determines its esr, both the size and the value will be larger than a ceramic capacitor that would give similar ripple performance. one benefit is that the larger capaci- tance may give better transient response for large changes in load current. table 2 lists several capacitor vendors. table 2. low esr surface mount capacitors vendor type series taiyo yuden ceramic x5r, x7r avx ceramic x5r, x7r tantalum tps kemet tantalum t491, t494, t495 ta organic t520 al organic a700 sanyo ta or al organic poscap panasonic al organic sp cap tdk ceramic x5r, x7r diode selection the catch diode (d1 from figure 1) conducts current only during switch off time. average forward current in normal operation can be calculated from: i d(avg) = i out (v in C v out )/v in the only reason to consider a diode with a larger current rating than necessary for nominal operation is for the worst-case condition of shorted output. the diode current will then increase to the typical peak switch current. peak reverse voltage is equal to the regulator input volt- age. use a diode with a reverse voltage rating greater than the input voltage. table 3 lists several schottky diodes and their manufacturers. operatio u
lt1943 14 1943fa r4 should be 10k ? or less to avoid bias current errors. if switcher 4 is used to generate a positive output voltage, nfb4 should be tied to fb4. regulating negative output voltages the lt1943 contains an inverting op amp with its non- inverting terminal tied to ground and its output connected to the fb4 pin. use this op amp to generate a voltage at fb4 that is proportional to v out4 . choose the resistors accord- ing to: r rv v ut 6 5 1 245 0 = ?| | . use 10k for r5. tie 10pf in parallel with r5. duty cycle range the maximum duty cycle (dc) of the lt1943 switching regulator is 85% for sw2, and 83% for sw3 and sw4. the duty cycle for a given application using the step-up or charge pump topology is: dc vv v out in out = ||C || the duty cycle for a given application using the inverter or sepic topology is: table 3. schottky diodes part number v r (v) i ave (a) v f at 1a (mv) v f at 2a (mv) on semiconductor mbrm120e 20 1 530 595 mbrm140 40 1 550 diodes inc. b120 20 1 500 b130 30 1 500 b220 20 2 500 b230 30 2 500 b240 40 2 500 international rectifier 10bq030 30 1 420 470 20bq030 30 2 470 boost pin considerations the minimum operating voltage of an lt1943 application is limited by the undervoltage lockout ~4v and by the maximum duty cycle. the boost circuit also limits the minimum input voltage for proper start-up. if the input voltage ramps slowly, or the lt1943 turns on when the output is already in regulation, the boost capacitor may not be fully charged. because the boost capacitor charges with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. this minimum load will depend on input and output voltages. the typical performance character- istics section shows a plot of the minimum load current to start as a function of input voltage for a 3.3v output. the minimum load current generally goes to zero once the circuit has started. even without an output load current, in many cases the discharged output capacitor will present a load to the switcher that will allow it to start. inverter/step-up considerations regulating positive output voltages the output voltage is programmed with a resistor divider between the output and the fb pin. choose the resistors according to: r3 = r4(v out /1.25 C 1) c1 10pf r6 r5 10k nfb4 fb4 1943 a2 Cv out r3 r4 fb4 1943 a1 v out nfb4 operatio u
lt1943 15 1943fa output capacitor selection use low esr (equivalent series resistance) capacitors at the output to minimize the output ripple voltage. multilayer ceramic capacitors are an excellent choice, as they have an extremely low esr and are available in very small pack- ages. x7r dielectrics are preferred, followed by x5r, as these materials retain their capacitance over wide voltage and temperature ranges. a 10 f to 22 f output capacitor is sufficient for most lt1943 applications. even less capacitance is required for outputs with |v out | > 20v or | i out | < 100ma. solid tantalum or os-con capacitors will also work, but they will occupy more board area and will have a higher esr than a ceramic capacitor. always use a capacitor with a sufficient voltage rating. diode selection a schottky diode is recommended for use with the lt1943 switcher 2 and switcher 4. the schottky diode for switcher 3 is integrated inside the lt1943. choose diodes for switcher 2 and switcher 4 rated to handle an average current greater than the load current and rated to handle the maximum diode voltage. the average diode current in the step-up, sepic, and inverting configurations is equal to the load current. each of the two diodes in the charge pump configurations carries an average diode current equal to the load current. the maximum diode voltage in the step-up and charge pump configurations is equal to |v out |. the maximum diode voltage in the sepic and inverting configurations is v in + |v out |. input capacitor selection bypass the input of the lt1943 circuit with a 4.7 f or higher ceramic capacitor of x7r or x5r type. a lower value or a less expensive y5v type will work if there is additional bypassing provided by bulk electrolytic capacitors or if the input source impedance is low. the following paragraphs describe the input capacitor considerations in more detail. step-down regulators draw current from the input supply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the lt1943 input and to force this switching current into a tight local loop, minimizing emi. the input capacitor dc v vv out in out = + || || the lt1943 can still be used in applications where the duty cycle, as calculated above, is above the maximum. how- ever, the part must be operated in discontinuous mode so that the actual duty cycle is reduced. inductor selection several inductors that work well with the lt1943 regulator are listed in table 4. besides these, many other inductors will work. consult each manufacturer for detailed informa- tion and for their entire selection of related parts. use ferrite core inductors to obtain the best efficiency, as core losses at frequencies above 1mhz are much lower for ferrite cores than for powdered-iron units. a 10 h to 22 h inductor will be the best choice for most lt1943 step-up and charge pump designs. choose an inductor that can carry the entire switch current without saturating. for inverting and sepic regulators, a coupled inductor, or two separate inductors is an option. when using coupled inductors, choose one that can handle at least the switch current without saturating. if using uncoupled inductors, each inductor need only handle approximately one-half of the total switch current. a 4.7 h to 15 h coupled inductor or two 10 h to 22 h uncoupled inductors will usually be the best choice for most lt1943 inverting and sepic designs. table 4. inductors. part number value ( h) i rms (a) dcr ( ? ) height (mm) coiltronics tp3-4r7 4.7 1.5 0.181 2.2 tp4-100 10 1.5 0.146 3.0 sumida cd73-100 10 1.44 0.080 3.5 cdrh5d18-6r2 6.2 1.4 0.071 2.0 cdrh4d28-100 10 1.3 0.048 3.0 cdrh4d28-100 10 1.0 0.095 3.0 coilcraft do3314-103 10 0.8 0.520 1.4 1008ps-103 10 0.78 0.920 2.8 operatio u
lt1943 16 1943fa must have low impedance at the switching frequency to do this effectively and it must have an adequate ripple current rating. the input capacitor rms current can be calculated from the step-down output voltage and current, and the input voltage: ci vvv v i inrms out out in ut in out =< ? (C ) 0 2 and is largest when v in = 2 v out (50% duty cycle). the ripple current contribution from the other channels will be minimal. considering that the maximum load current from switcher 1 is ~2.8a, rms ripple current will always be less than 1.4a. the high frequency of the lt1943 reduces the energy storage requirements of the input capacitor, so that the capacitance required is less than 10 f. the combination of small size and low impedance (low equivalent series resistance or esr) of ceramic capacitors makes them the preferred choice. the low esr results in very low voltage ripple. ceramic capacitors can handle larger magnitudes of ripple current than other capacitor types of the same value. use x5r and x7r types. an alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor, for ex- ample a 1 f ceramic capacitor in parallel with a low esr tantalum capacitor. for the electrolytic capacitor, a value larger than 10 f will be required to meet the esr and ripple current requirements. because the input capacitor is likely to see high surge currents when the input source is applied, only consider a tantalum capacitor if it has the appropriate surge current rating. the manufacturer may also recommend operation below the rated voltage of the capacitor. be sure to place the 1 f ceramic as close as possible to the v in and gnd pins on the ic for optimal noise immunity. a final caution is in order regarding the use of ceramic capacitors at the input. a ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. if power is applied quickly (for example by plug- ging the circuit into a live power source), this tank can ring, doubling the input voltage and damaging the lt1943. the solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor (an electrolytic) in parallel with the ceramic capacitor. for details, see appli- cation note 88. soft-start and shutdown the run/ss (run/soft-start) pin is used to place the switching regulators and the internal bias circuits in shut- down mode. it also provides a soft-start function, along with ss-234. if the run/ss is pulled to ground, the lt1943 enters its shutdown mode with all regulators off and quiescent current reduced to ~35 a. an internal 1.7 a current source pulls up on the run/ss and ss-234 pins. if the run/ss pin reaches ~0.8v, the internal bias circuits start and the quiescent currents increase to their nominal levels. if a capacitor is tied from the run/ss or ss-234 pins to ground, then the internal pull-up current will generate a voltage ramp on these pins. this voltage clamps the v c pin, limiting the peak switch current and therefore input current during start-up. the run/ss pin clamps v c1 , and the ss-234 pin clamps the v c2 , v c3 , and v c4 pins. a good value for the soft-start capacitors is c out /10,000, where c out is the value of the largest output capacitor. to shut down sw2, sw3, and sw4, pull the ss-234 pin to ground with an open drain or collector. if the shutdown and soft-start features are not used, leave the run/ss and ss-234 pins floating. v on pin considerations the v on pin is the delayed output for switching regulator 3. when the c t pin reaches 1.1v, the output disconnect pnp turns on, connecting v on to e3. the v on pin is current limited, and will protect the lt1943 and input source from a shorted output. however, if the v on pin is charged to a high output voltage, and then shorted to ground through a long wire, unpredictable results can occur. the resonant tank circuit created by the inductance of the long wire and the capacitance at the v on pin can ring the v on pin several volts below ground. this can lead to large and potentially damaging currents internal to the lt1943. if the v on output may be shorted after being fully charged, there operatio u
lt1943 17 1943fa should be 5 ? of resistance between the v on pin and its connection to the load, as shown on figure 3. the resis- tance will damp resonant tank circuit created by the output short. as the transient on the v on pin during a short-circuit condition will be highly dependent on the layout and the type of short, be sure to test the short condition and examine the voltage at the v on pin to check that it does not swing below ground. c1 0.47 f r1 5 ? v on r1 is only necessary if load may have transient short condition. otherwise, connect v on pin directly to load to load 1943 f03 printed circuit board layout for proper operation and minimum emi, care must be taken during printed circuit board (pcb) layout. figure 4 shows the high-current paths in the step down regulator circuit. note that in the step-down regulators, large, switched currents flow in the power switch, the catch diode, and the input capacitor. in the step-up regulators, large, switched currents flow through the power switch, the switching diode, and the output capacitor. in sepic and inverting regulators, the switched currents flow through the power switch, the switching diode, and the tank capacitor. the loop formed by the components in the switched current path should be as small as possible. place these components, along with the inductor and output capacitor, on the same side of the circuit board, and connect them on that layer. place a local, unbroken ground plane below these components, and tie this ground plane to system ground at one location, ideally at the ground terminal of the output capacitor c2. additionally, keep the sw and boost nodes as small as possible. thermal considerations the pcb must provide heat sinking to keep the lt1943 cool. the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should be tied to other copper layers below with thermal vias; these layers will spread the heat dissipated by the lt1943. place additional vias near the catch diodes. adding more copper to the top and bottom layers and tying this copper to the internal planes with vias can reduce thermal resistance further. with these steps, the thermal resistance from die (or junction) to ambient can be reduced to ja = 25 c or less. with 100lfpm airflow, this resistance can fall by another 25%. further increases in airflow will lead to lower thermal resistance. v in sw gnd (a) v in v sw c1 d1 c2 1943 f04 l1 sw gnd (c) v in sw gnd (b) i c1 figure 4. subtracting the current when the switch is on (a) from the current when the switch is off (b) reveals the path of the high frequency switching current (c) keep this loop small. the voltage on the sw and boost nodes will also be switched; keep these nodes as small as possible. finally, make sure the circuit is shielded with a local ground plane figure 3. transient short protection for v on pin operatio u
lt1943 18 1943fa figure 5. top side pcb layout typical applicatio s u operatio u v c2 v c3 sw4 nfb4 fb4 bias boost sw1 fb1 v c1 sw2 fb2 run-ss ss-234 c t v on e3 fb3 gnd lt1943 v in sw3 6.8k 18k 27k 2.2nf 2.2nf 680pf 100pf 100pf 100pf 16.2k 10.0k 10.0k 44.2k 274k 10.0k 10pf 10.0k 4.7 h 0.22 f 10v x5r cmdsh-3 v logic 3.3v 2a 10 f 25v x5r 0.47 f 16v x5r zhcs400 zhcs400 b240a v off C5.5v 50ma 33 h 10 h 10 h 10 h 88.7k 10 f 16v x5r 2.2 f 50v x5r 0.47 f 50v x5r 13k 2.2nf 100pf av dd 12.2v 500ma v on 35v 30ma 1943 ta02 2.2 f 10v x5r v in 8v to 20v 22 f 6.3v x5r 0.015 f 0.015 f 0.047 f b230a v c4 sgnd pgood 1 f 25v x5r pgood 8v to 20v input, quad output tft-lcd power supply 1943 f05 gnd place vias under ground pad to ground plane for good thermal conductivity v in av dd v off gnd v logic
lt1943 19 1943fa package descriptio u fe28 (eb) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8910 11 12 13 14 19 20 22 21 15 16 18 17 9.60 C 9.80* (.378 C .386) 4.75 (.187) 2.74 (.108) 28 2726 25 24 23 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 0.195 C 0.30 (.0077 C .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation eb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
lt1943 20 1943fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2003 lt/lt 0405 rev a ? printed in usa related parts part number description comments lt1615/lt1615-1 300ma/80ma (i sw ), constant off-time, high efficiency v in : 1.2v to 15v, v out(max) : 34v, i q : 20 a, i sd : <1 a, step-up dc/dc converters thinsot tm package lt1940 dual output 1.4a (i out ), constant 1.1mhz, high efficiency v in : 3v to 25v, v out(min) : 1.2v, i q : 2.5ma, i sd : <1 a, step-down dc/dc converter tssop-16e package lt1944/lt1944-1 dual output 350ma (i sw ), constant off-time, high efficiency v in : 1.2v to 15v, v out(max) : 34v, i q : 20 a, i sd : <1 a, step-up dc/dc converter ms package lt1945 dual output, pos/neg, 350ma (i sw ), constant off-time, v in : 1.2v to 15v, v out(max) : 34v, i q : 20 a, i sd : <1 a, high efficiency step-up dc/dc converter ms package lt1946/lt1946a 1.5ma (i sw ), 1.2mhz/2.7mhz, high efficiency v in : 2.75v to 16v, v out(max) : 34v, i q : 20 a, i sd : <1 a, step-up dc/dc converter ms package lt1947 1.1a, 3mhz, tft-lcd triple output switching regulator v in : 2.7v to 8v, v out(max) : 34v, i q : 9.5ma, i sd : <1 a, ms package lt3464 85ma (i sw ), constant off-time, high efficiency step-up dc/dc v in : 2.3v to 10v, v out(max) : 34v, i q : 25 a, i sd : <0.5 a, converter with integrated schottky and output disconnect pnp thinsot package thinsot is a trademark of linear technology corporation. typical applicatio u 5v input, quad output tft-lcd power supply v c2 v c3 sw4 nfb4 fb4 bias boost sw1 fb1 v c1 sw2 fb2 run-ss ss-234 c t v on e3 fb3 gnd lt1943 v in sw3 4.7k 7.5k 30k 4700pf 2.7nf 1500pf 100pf 100pf 100pf 16.5k 10.0k 10.0k 80.6k 232k 10.0k 10pf 10.0k 4.7 h 0.22 f 10v x5r cmdsh-3 v logic 3.3v 1.5a 10 f 10v x5r zhcs400 zhcs400 b240a v off C10v 50ma 68 h 4.7 h 10 h 95.3k 100k si2343ds 10 f 16v x5r 2.2 f 35v x5r 0.47 f 35v x5r 13k 2.2nf 100pf av dd 13v 500ma v on 30v 20ma 1943 ta03 2.2 f 10v x5r v in 4.5v to 8v 22 f 10v x5r 0.015 f 0.015 f 0.047 f b230a v c4 sgnd pgood 0.47 f 16v x5r

▲Up To Search▲

Price & Availability of LT19431

	To Download LT19431 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .